1. Field of the Invention
The present invention relates to high density memory devices, and particularly to memory devices in which multiple planes of memory cells are arranged to provide a three-dimensional memory array.
2. Description of Related Art
In an example three-dimensional memory array, multiple ridges each include alternating stacks of semiconductor strips and oxide strips, and the ridges are covered by charge storage layers such as polysilicon or charge trapping dielectric material like ONO. Word lines orthogonal to and conformal to the ridges access the memory cells in the three-dimensional memory array. Insulating lines, such as oxide lines orthogonal to and conformal to the ridges, electrically isolate the neighboring word lines from each other.
However, it is not trivial to form the oxide lines between the word lines such that neighboring word lines are electrically isolated from each other by the oxide lines. FIGS. 1-2 show problems in various manufacturing processes for the word lines and the oxide lines of a three-dimensional memory array.
FIG. 1 is a perspective illustration of a three dimensional memory array device, where the polysilicon word lines are formed prior to the oxide lines separating the word lines, and polysilicon residue forms an undesirable bridge electrically connecting neighboring word lines.
Semiconductor strips 11, 13, and 15 are separated by oxide strips 10, 12, 14, and 16. The stacks of alternating semiconductoroxide strips are covered by charge storage layers 26, such as ONO or ONONO. The polysilicon word line 55 is formed by covering the stacks of alternating semiconductoroxide strips and charge storage layers with polysilicon, and etching away excess polysilicon between neighboring polysilicon word lines to form trenches between neighboring polysilicon word lines. After etching away the excess polysilicon, oxide lines are formed that isolate neighboring polysilicon word lines.
A high aspect ratio is presented by the height of the stacks of alternating semiconductoroxide strips covered by charge storage layers, relative to the desired distance between neighboring word lines. As a result, there is a failure to etch away polysilicon residue 56. Despite the following oxide fill in the trenches formed by the polysilicon etch, the polysilicon residue 56 electrically connects neighboring word lines (the word line shown in the figure, and a neighboring word line not shown in the figure).
The charge storage layers fill part of the oxide void in the stack of alternating semiconductoroxide strips, which is a region 27 of oxide pull-back. Oxide pull-back was caused by cleaning the stacks of alternating semiconductoroxide strips, in preparation for making the charge storage layers. The region 27 of oxide pull-back in turn results in a void in the charge storage layers. This void is filled by polysilicon residue 57, which electrically connects neighboring word lines (the word line shown in the figure, and another neighboring word line not shown in the figure).
FIG. 2 is a perspective illustration of a three dimensional memory array device, where the oxide lines are formed prior to the polysilicon word lines, and an oxide void allows polysilicon residue to form an undesirable bridge electrically connecting neighboring word lines.
Semiconductor strips 11, 13, 15 are separated by oxide strips 10, 12, 14, 16. The stacks of alternating semiconductoroxide strips are covered by charge storage layers, such as a charge storage structure of an oxide 20-nitride 21-oxide 22. The oxide line 45 is formed by covering the stacks of alternating semiconductoroxide strips and charge storage layers with oxide, and etching away excess oxide between neighboring oxide lines to form trenches between neighboring oxide lines. After etching away the excess oxide, damascene polysilicon word lines are formed in the trenches between neighboring oxide lines.
Oxide line 45 has a void 46. In the step of making polysilicon word lines in the trenches between neighboring oxide lines, the oxide void 46 is filled with polysilicon, electrically connecting the neighboring polysilicon word lines on either side of the oxide line 45.
An additional problem is the quality of the charge storage layers covering the alternating stacks of semiconductor strips and oxide strips. When the charge storage layers are formed prior to the word lines and oxide lines, and the oxide lines are formed prior to the word lines, the oxide lines are formed by etching away excess oxide between the oxide lines to form trenches for the word lines. However, after the oxide etch removes excess oxide, the oxide etch damages the charge storage layers under the excess oxide. This damage to the charge storage layers harms memory device performance. For charge storage layers with an outer oxide such as ONO, it is difficult to selectively etch the excess oxide but not the outer oxide of the charge storage layers.
FIG. 3 is a top view of a three dimensional memory array device, where the ONO storage layers are formed after the oxide lines but prior to the polysilicon word lines, resulting in larger dimensions of the array. The process flow shows: (i) formation of the stacks of alternating oxidesemiconductor strips 18, (ii) formation of oxide lines 42 orthogonal and conformal to the oxidesemiconductor strips, and (iii) formation of charge storage layers 28 such as ONO or polysilicon. The charge storage layers can cover the stacks of alternating oxidesemiconductor strips 18. The figure does not show the charge storage layers can cover the stacks of alternating oxidesemiconductor strips 18, so that the lateral dimensions of the storage layers are visible. This process flow is disadvantageous, because the unit cell size is laterally enlarged by twice the thickness of the storage layers.
U.S. application Ser. No. 12347,331 filed 10 Jan. 2012 describes a damascene word line. The present application describes additional technology regarding a damascene word line. Several embodiments in U.S. application Ser. No. 12347,331 have a relatively shorter process flow. Several embodiments of the present application can be scaled down to a relatively smaller word line pitch, or relatively smaller distance between neighboring word lines.
It is desirable to provide a structure for three-dimensional integrated circuit memory with a low manufacturing cost, including reliable, very small memory elements and improved process window associated with neighboring stacks of memory cell strings having gate structures.